Microprocessor without Interlocked Pipeline Stages - définition. Qu'est-ce que Microprocessor without Interlocked Pipeline Stages
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Qu'est-ce (qui) est Microprocessor without Interlocked Pipeline Stages - définition

RESEARCH PROJECT AT STANFORD UNIVERSITY THAT WAS COMMERCIALIZED BY MIPS COMPUTER SYSTEMS
Microprocessor without Interlocked Pipeline Stages

Microprocessor without Interlocked Pipeline Stages         
<processor> (MIPS) A project at Stanford University intended to simplify processor design by eliminating hardware interlocks between the five pipeline stages. This means that only single execution cycle instructions can access the thirty two 32-bit general registers, so that the compiler can schedule them to avoid conflicts. This also means that LOAD/STORE and branch instructions have a one-cycle delay to account for. However, because of the importance of multiply and divide instructions, a special HI/LO pair of multiply/divide registers exist which do have hardware interlocks, since these take several cycles to execute and complicate instruction scheduling. The project eventually lead to the commercial MIPS R2000 processor. (1995-02-09)
Pipeline (computing)         
DATA PROCESSING CHAIN
CPU pipeline; Pipeline architecture; Pipeline (computer); Pipelining (software); Pipelining (computing); Pipeline parallelism; Pipeline Parallelism; Reservation table; Data pipeline
In computing, a pipeline, also known as a data pipeline,Data Pipeline Development Published by Dativa, retrieved 24 May, 2018 is a set of data processing elements connected in series, where the output of one element is the input of the next one. The elements of a pipeline are often executed in parallel or in time-sliced fashion.
Pipeline transport         
  • The world's longest ammonia pipeline from Russia to [[Ukraine]]
  • Scenario for benzene leaching to groundwater
  • An underground petroleum pipeline running through a park
  • date=2011-07-06}} Paper in German. Retrieved 2010-09-20</ref>
  • Gas pipe in the dry region of Antofagasta, Chile.
  • The [[Los Angeles Aqueduct]] in [[Antelope Valley]].
  • date=April 2022}} Deliveries on some pipelines were disrupted by or became controversial after the [[2022 Russian invasion of Ukraine]], including the [[2022 Russia–European Union gas dispute]].
  • The SCADA System for pipelines.
  • Alaska Pipeline]].
  • Pig]]" launcher/receiver, on the natural gas pipeline in Switzerland
  • Thor Pipeline in [[Randers]], Denmark
  • The Trans Alaska Pipeline crossing under the [[Delta River]] and over ridge of the [[Alaska Range]]
MODE OF TRANSPORT USING SEALED PIPES
Oil pipeline; Pipeline transportation; Gas pipeline; Oil pipelines; Fossil gas pipeline; Natural gas line; High pressure gas pipeline; Gas pipe; Gas main; Natural gas pipeline; Gas grid; Oleoduct; Natural gas grid; Methane grid; Petroleum pipeline; Transport pipeline; Pipelined Natural Gas; Pipelined natural gas; Crude Oil Pipelines; Product Pipelines; Pipeline accident; Pipeline safety
Pipeline transport is the long-distance transportation of a liquid or gas through a system of pipes—a pipeline—typically to a market area for consumption. The latest data from 2014 gives a total of slightly less than of pipeline in 120 countries of the world.

Wikipédia

Stanford MIPS

MIPS, an acronym for Microprocessor without Interlocked Pipeline Stages, was a research project conducted by John L. Hennessy at Stanford University between 1981 and 1984. MIPS investigated a type of instruction set architecture (ISA) now called reduced instruction set computer (RISC), its implementation as a microprocessor with very large scale integration (VLSI) semiconductor technology, and the effective exploitation of RISC architectures with optimizing compilers. MIPS, together with the IBM 801 and Berkeley RISC, were the three research projects that pioneered and popularized RISC technology in the mid-1980s. In recognition of the impact MIPS made on computing, Hennessey was awarded the IEEE John von Neumann Medal in 2000 by the Institute of Electrical and Electronics Engineers (IEEE) (shared with David A. Patterson), the Eckert–Mauchly Award in 2001 by the Association for Computing Machinery, the Seymour Cray Computer Engineering Award in 2001 by the IEEE Computer Society, and, again with David Patterson, the Turing Award in 2017 by the ACM.

The project was initiated in 1981 in response to reports of similar projects at IBM (the 801) and the University of California, Berkeley (the RISC). MIPS was conducted by Hennessy and his graduate students until its conclusion in 1984. Hennessey founded MIPS Computer Systems in the same year to commercialize the technology developed by the project. In 1985, MIPS Computer Systems announced a new ISA, also called MIPS, and its first implementation, the R2000 microprocessor. The commercial MIPS ISA, and its implementations went on to be widely used, appearing in embedded computers, personal computers, workstations, servers, and supercomputers. As of May 2017, the commercial MIPS ISA is owned by Imagination Technologies, and is used mainly in embedded computers. In the late 1980s, a follow-up project called MIPS-X was conducted by Hennessy at Stanford.

The MIPS ISA was based on a 32-bit word. It supported 32-bit addressing, and was word-addressed. It was a load/store architecture—all references to memory used load and store instructions that copied data between the main memory and 32 general-purpose registers (GPRs). All other instructions, such as integer arithmetic, operated on the GPRs. It possessed a basic instruction set consisting of instructions for control flow, integer arithmetic, and logical operations. To minimize pipeline stalls, all instructions except for load and store had to be executed in one clock cycle. There were no instructions for integer multiplication or division, or operations for floating-point numbers. The architecture exposed all hazards caused by the five-stage pipeline with delay slots. The compiler scheduled instructions to avoid hazards resulting in incorrect computation whilst simultaneously ensuring that the generated code minimized execution time. MIPS instructions are 16 or 32 bit long. The decision to expose all hazards was motivated by the desire to maximize performance by minimizing critical paths, which interlock circuits lengthened. Instructions were packed into 32-bit instruction words (as MIPS is word-addressed). A 32-bit instruction word could contain two 16-bit operations. These were included to reduce the size of machine code. The MIPS microprocessor was implemented in NMOS logic.